LEDA BS studies

PREDAVANJA, UPUTSTVA I DRUGI DOKUMENTI POTREBNI STUDENTIMA

Projektovanje elektronskih kola (Elektronika - EKS)

prof. dr Predrag Petković
doc. dr Miljana Milić

Pitanja i sugestije profesoru

Obaveštenje
 
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Rezultati ispita u poslednjem ispitnom roku

 
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Ispit

 

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Literatura

 

 

Predavanja

Najnovija (2016/17)

Godina 2015/16

Vežbe

On-line tutoriali

  1. Lesson 4 - VHDL Example 1: 2-Input Gates
  2. Lesson 11 - VHDL Example 3: Majority Circuit
  3. Lesson 12 - VHDL Example 4: 2-Bit Comparator
  4. Lesson 18 - VHDL Example 6: 2-to-1 MUX - if statement
  5. Lesson 24 - 7-segment Displays
  6. Lesson 25 - VHDL Example 12: 7-Segment Decoder using Logic Equations
  7. Lesson 26 - VHDL Example 13: 7-Segment Decoder-case Statement
  8. Lesson 37 - VHDL Example 21: N-Bit Comparator - Relational Operators
  9. Lesson 39 - VHDL Example 22: 3-to-8 Decoder using Logic Equations
  10. Lesson 40 - VHDL Example 23: 3-to-8 Decoder using a for-loop
  11. Lesson 45a - Adders
  12. Lesson 45b - Adders Carry and Overflow
  13. Lesson 46 - Example 27: 4-Bit Adder using Logic Equations
  14. Lesson 52 - Shifters
  15. Lesson 60 - Example 36: 4-bit Arithmetic/Logic Unit ALU
  16. Lesson 63 - Example 38: Edge-triggered D Flip-Flop with Set and Clear
  17. Lesson 64 - Example 39: D Flip-Flops in VHDL
  18. Lesson 65 - Example 40: D Flip-Flops with Clear and Set
  19. Lesson 68 - Example 42: 1-Bit Register
  20. Lesson 69 - Example 43: 4-Bit Register

Studenstki projekti

 

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