PPT Slide

ime_signala <= [transport | quarded]

talasni_oblik_1 when uslov_1 else

…

talasni_oblik_N-1 when uslov_N-1 else

talasni_oblik_N;

architecture Conditional of AND_Gate is

begin

Y <= ‘1’ after Delay when A = ‘1’ and B = ‘1’ else

‘0’ after Delay;

end Conditional;