PPT Slide
arcitecture behaviour of count2 is
begin
count_up : process (clock)
variable count_value : natural := 0;
begin
if clock = ‘1’ then
count_value := (count_value + 1) mod 4;
q0 <= bit’val(count_value mod 2) after prop_delay;
q1 <= bit’val(count_value /2 ) after prop_delay;
end if;
end process;
end behaviour;
OPIS PONA[ANJA
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