PPT Slide

component t_flipflop

port (ck : in; q : out bit);

end component;

component inverter

port (a : in bit; y : out bit);

end component;

signal ff0, ff1, inv_ff0, : bit;

begin

bit_0 : t_flipflop port map(ck =>clock, q=>ff0);

inv : inverter port map(a=>ff0, y=>inv_ff0);

bit_1 : t_flipflop port map(ck=>inv_ff0, q=>ff1);

q0 <= ff0;

q1 <= ff1;

end structure;